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M8050A 误码仪 1至2 详细指标
High-speed receiver characterization for error-free data transmission
一、Data 输出特性 · M8042A（含） M8058A/M8059A 和高-电压远程 heads（表 1）
条件：M8068A/M8069A. Values apply at the end of the reference cable at the outputs of the remote heads.
Parameter Value (with M8059A / M8058A remote
Value (with M8069A / M8068A high-voltage
NRZ and PAM4)
2.0 to 120.0 GBd for M8042A-G12 (only with M8059A or M8069A)
2.0 to 64.8 GBd for M8042A-G64
2.0 to 32.4 GBd for M8042-G32
Data formats NRZ, PAM4 standard.
PAM3 (requires M8042A-0P3/UP3).
PAM6 (requires M8042A-0P6/UP6). The maximum supported symbol rate is
96 GBd, over-
PAM8 (requires M8042A-0P8/UP8). The maximum supported symbol rate is
80 GBd, over-
Channels per module 1 channel
2 AXIe slots (option M8042A-0G1)
2 channels
3 AXIe slots (option M8042A-0G2)
Amplitude M8059A:
100 mVpp to 1.6 Vpp differential
50 mVpp to 0.8 Vpp single-ended
M8069A:
1 Vpp to 3.6 Vpp up to 113.5 GBd differential
500 mVpp to 1.8 Vpp up to 113.5 GBd single-
ended 1 Vpp to 3.4 Vpp from >113.5 to 116 GBd differential 500 mVpp to 1.7 Vpp from >
113.5 to 116 GBd
M8058A:
100 mVpp to 1.8 Vpp differential
50 mVpp to 0.9 Vpp single-ended
M8068A:
1 Vpp to 5 Vpp differential
500 mVpp to 2.5 Vpp single-ended
Amplitude resolution 1 mV
3 mV
Amplitude accuracy ±10% ±10 mV typical (AC) 1 ±10% ±30 mV typical (AC)
1
Symbol level resolution PAM levels are adjustable in 0.1% steps of amplitude
Coupling DC/AC-coupled (selectable) AC-coupled only
Output voltage window
–1 to +3.0 V depends on external
Common mode voltage accuracy 25 mV + 12.5%
5 Not applicable
–1 to +3.0 V
条件：To protect the output stage, the output is disabled when an unexpected voltage or termination impedance is detected.
DC-coupled mode: Termination range for devices connected to data out:
Unbalanced 50 Ω
+15 Ω / –10 Ω
Typical balanced 100 Ω
±30 Ω typical
Operation into open is possible for following ranges when DC-coupled and 50 Ω
+15 Ω / –10 Ω
Parameter Value (with M8059A / M8058A remote
条件：Intrinsic total jitter 6 For M8009A with option -062:
Value (with M8069A / M8068A high-voltage
remote heads) balanced termination modes are selected and M8042A module driver
Output amplitude max.
450 mV
Transition time (20% to 80%)
M8059A:
4 ps typical at 120 GBd
6.5 ps typical at 64 GBd
8 ps typical at 8 GBd
M8069A:
4.5 ps typical at 120 GBd
7.5 ps typical at 64 GBd
11 ps typical at 8 GBd
M8058A:
7 ps typical at 64 GBd
8.5 ps typical at 8 GBd
M8068A:
6.5 ps typical at 64 GBd
9 ps typical at 32 GBd
10 ps typical at 8 GBd
3.3 ps typical
6 ps typical for symbol rates from 2 to 20 GBd
For M8009A with option
-061:
3.3 ps typical in combination with M8009A-061
7 ps typical for symbol rates from 70 to 80 GBd
6 ps typical for symbol rates from 16 to 33 GBd
7 ps typical for symbol rates from 10 to 16 GBd
9 ps typical for symbol rates from 2 to 10 GBd
条件：means that first eye can be up to 50 mUI or 4 ps longer or shorter than subsequent eye.
For M8009A with option
-062:
6 mUI rms typical for symbol rates from 2 to 40 GBd
7 mUI rms typical for symbol rates from 40 to 64.5 GBd
10 mUI rms typical for symbol rates from 64.5 to 110 GBd
12 mUI rms typical for symbol rates from 110 to 120 GBd
For M8009A with option
-061:
10 mUI rms typical
15 mUI rms typical for symbol rates from 105 to 120 GBd
20 mUI rms typical for symbol rates from 99 to <105 GBd
40 mUI rms typical for symbol rates from 70 to 80 GBd
15 mUI rms typical for symbol rates from 30 to 33 GBd
7 mUI rms typical for symbol rates from 24 to 30 GBd
Clock/2 jitter range ±50 mUI or ±4 ps typical (whatever is less) for symbol rates above
7.9 GBd. Note: this
Adjustable clock/2 For each channel independently
M8059A:
M8069A:
M8058A:
53 to 58 GBd
37 dB typical
M8068A:
53 to 58 GBd
37 dB typical
Level random noise M8059A:
53.125 GBd
4.75 mV rms differential typical
106.25 GBd
6 mV rms differential typical
M8069A:
53.125 GBd
14 mV rms differential typical
106.25 GBd
20 mV rms differential typical
Parameter Value (with M8059A / M8058A remote
Value (with M8069A / M8068A high-voltage
M8058A:
53 to 58 GBd
5.5 mV rms differential typical
M8068A:
53 to 58 GBd
16 mV rms differential typical
Data delay Delay range
100 ns
Delay accuracy: ± (maximum (1.5 ps or 25 mUI whatever is higher) +
1% of entered value)
Skew between normal and complement 2 ps maximum at the end of the reference cable pair. Fixed.
1 ps maximum at connector of remote head
Reference cable pairs M8059A-801 and M8058A-801 have
1 ps of skew
Skew between data output
1 and 2 in one
条件：within 1 UI. Normal and complement output have same level (Max – Min)/2.
Repeatability: <
1 ps typical
Absolute skew: <
10 ps measured
Skew between data outputs of two M8042A modules
Repeatability: <
15 ps typical
Absolute skew: <
15 ps measured
Electrical idle (squelch) The output transitions from full swing to 0 V amplitude and vice versa at constant offset
Squelch granularity Pattern Editor (NRZ only): bit granularity
When controlled from sequencer: sequencer block wise
Automatic eye performance (de- emphasis) optimization by using an external
Yes, it requires the M8070ADVB plugin and an external Keysight DCA sampling oscilloscope
(refer to the Automatic De-emphasis Optimization section)
Connector type at data outputs of M8042A
1.00 mm, female
1.00 mm, female
1.85 mm, female
Reference cables M8059A:
Matched cable pair
1.00 mm (m) to 1.00
mm (m), 150 mm length
1 ps skew:
M8059A-801 (also orderable as M8059-
61621)
M8069A:
Matched cable pair
1.00 mm (m) to 1.00 mm
(m), 150 mm length
1 ps skew: M8059A-801
(also orderable as M8059-61621)
M8058A:
Matched cable pair
1.85 mm (m) to 1.85
mm (m), 150 mm length
1 ps skew:
M8058A-801 (also orderable as M8199-
61610)
M8068A:
Matched cable pair
1.85 mm (m) to 1.85 mm
(m), 150 mm length
1 ps skew: M8058A-801
(also orderable as M8199-61610).
条件：1. At 5 GBd measured with DCA -X N1046A and clock pattern and in the middle of the eye .
2. High level voltage range= 2/3* Vterm - 0.95 V < HIL < Vterm + 2 V. Low level voltage range= 2/3 * Vterm - 1 V < LOL <
3. Measurement procedure according to section 120D.3.1.6 of the IEEE 802.3 specification . The randomizer typically
which improves SNDR when the system is distortion ‑limited — especially at ultra ‑high symbol rates (>100 GBd).
4. Measured at 90% of maximum amplitude .
5. Common mode voltage = 0.5 * (measured offset at Normal + measured offset at Complement). Measured with the N1000A
6. Measured with the N1000A DCA with the N1060A module and PTB signal from Ref ClkOut 16G from M8009A, NRZ, PRBS1 5
GBd remote head. Output amplitude is set to 1.0 Vpp differential and the pattern is PRBS 215-1. Measured with
the DCA-X sampling oscilloscope N1000A with the N1046A electrical module.
Not applicable In case you need to protect inputs of an oscilloscope, e.g. DCA module N1046A
For M8069A
10 dB attenuator with 1.00 mm
For M8068A
10 dB attenuator with 1.85 mm
Pre-requisites Not applicable M8042A module driver
4.5 or higher.
improve s SNDR of for the M8059A and M8069A by 1 dB above
100 GBd. The randomizer is a scrambling process that
decorrelates data from hardware nonidealities, converting coherent, pattern ‑dependent distortion into broadband noise,
DCA with the N1046A module and a
10 dB attenuator.
Figure 5. Clean 112 GBd PAM4 output signal of the M8042A pattern generator module with the M8059A
120
条件：in high‑speed serial standards without requiring external signal conditioning components.
Impulse Response (FIR). Users can enter the de-emphasis in coefficient values.
The M8042A high‑performance pattern generator module provides built‑in transmitter
de‑emphasis, enabling realistic signal conditioning directly at the pattern generator output. This
capability allows users to compensate for channel loss and emulate transmitter behavior specified
The M8042A provides built-in de-emphasis with positive and negative cursors based on a Finite
二、De-emphasis characteristics for M8042A. Requires Option -0G4（表 2）
条件：1. Sum of all cursors absolute values may not exceed 1.0. Each absolute value of a cursor must be < than the value of the
De-emphasis Range if used as cursor Range if used as main cursor
De-emphasis taps 7, can be adjusted for each channel independently
1 UI spacing
Preset table
50 presets editable in xml file
Cursor (c0) 0.0 to ±0.45
1
Cursor (c1) 0.0 to ±0.45
1
Cursor (c2) 0.0 to ±0.45 1 0.3 to 1.0
1
Cursor (c3) 0.0 to ±0.45 1 0.3 to 1.0
1
Cursor (c4) 0.0 to ±0.45 1 0.3 to 1.0
1
Cursor (c5) 0.0 to ±0.45
1
Cursor (c6) 0.0 to ±0.45
1
Cursor coefficient resolution 0.004 Hardware capable resolution, user interface allows
0.001 steps
Main cursor Configurable position between c2 and c4
Figure
6. The pattern generator provides built-in de-emphasis to emulate a TX equalizer. The example shows
a configuration for IEEE
802.3ck with three pre-cursors c(-3), c(-2), c(-1), the main cursor c(0), and one post
cursor c(1).
Automatic De-emphasis Optimization
The Automatic De‑emphasis Optimization feature (also referred to as “Auto De‑emphasis”)
optimizes the de‑emphasis settings at the pattern generator output (remote head) to achieve
optimal eye performance for NRZ or PAM4 signals. In addition, the feature supports cable and
fixture de‑embedding or embedding using imported S‑parameter files.
To use this feature with the M8042A pattern generator module in combination with the M8058A,
M8059A, M8068A, or M8069A remote head, the M8070ADVB Advanced Measurement Package
plugin must be installed and licensed in the M8070B software.
One of the following DCA‑X configurations is required
• Keysight 86100D Infiniium DCA-X Wide-Bandwidth Oscilloscope equipped with the
86108B
条件：• Keysight N1000A DCA-X Wide-Bandwidth Oscilloscope Mainframe equipped with:
o N1030A 65 GHz optical or one 65 GHz optical and one 95 GHz electrical channel module.
o N1046A 75/85/100 GHz, 1/2/4 Port, Electrical Remote Sampling Head module.
• Keysight N1092C DCA-M Sampling Oscilloscope (One Optical and Two Electrical Channels).
• Keysight N1092E DCA-M Sampling Oscilloscope (Two Optical and Two Electrical Channels).
o N1060A 50/85 GHz
64 GBd Precision Waveform Analyzer module.
o N1032A/B
90/120 GHz Single Channel Optical module.
• Keysight N1094A/B
2/4 Channel Electrical DCA-M Oscilloscope.
• Keysight N1093A/B Single-Mode Optical DCA-M Sampling Oscilloscope.
For more details and how to set this configuration up, refer to the M8070ADVB Advanced
Measurement Package User Guide
Figure 7. Principle connection diagram for automatic de‑emphasis optimization using the M8042A pattern
generator and N1000A DCA‑X. Physical connections are simplified.
De-emphasis Presets for PCIe Testing
PCIe Tx equalization (TxEQ) de‑emphasis presets are standardized transmitter‑side settings that
define predefined combinations of pre‑cursor, main cursor, and post‑cursor tap weights to
compensate for frequency‑dependent channel loss
Introduced in Gen3 and used through Gen6 and beyond, these presets provide coarse transmit
equalization options spanning short, low‑loss links to long, highly lossy channels, enabling
interoperable and fast link training without full continuous tuning. During link equalization, the
transmitter advertises its supported presets, the receiver evaluates their signal quality and then
selects (and optionally fine-tunes around) the best preset to minimize intersymbol interference
(ISI) while maintaining constant signal swing, ensuring reliable eye opening and BER performance
across diverse PCIe interconnect topologies
In the M8070B software, if the PHY protocol mode PCIe3, PCIe4, PCIe5, or PCIe6 for the pattern
generator sequence is selected, the de-emphasis capabilities are switched from the multi-tap FIR
to the PCI Express type of FIR editor with coefficient entry as integers dependent of the selected
条件：A full swing from 24 to 63 coefficient resolution steps can be selected.
Figure
8. PCIe TxEQ matrix editor can be accessed if the PHY protocol mode PCIe3, PCIe4, PCIe5, PCIe6 is
Forward Error Correction (FEC) Encoding
条件：With option M8042A‑0G9, users can inject errors pre‑ and post‑FEC to validate receiver FEC
The Keysight M8042A pattern generator module supports native Forward Error Correction (FEC)
encoding and precoding in accordance with IEEE 802.3cd and IEEE
802.3dj specifications
enabling realistic, PHY‑compliant stimulus generation for advanced Ethernet interfaces. It
implements Reed‑Solomon FEC (RS‑FEC) for 100GBASE‑R
200GBASE‑KP4, and
2×400GBASE‑KP4 at the PCS layer, including standards‑compliant codeword framing, parity
generation, and lane alignment. For KP4‑based interfaces, mandatory precoding is supported to
mitigate error propagation and improve post‑FEC BER performance.
decoding. The module operates at 53.125 GBd per lane for 100G‑1 KP4
200G‑2 KP4, and
2×400G‑4 KP4, and at 106.25 GBd per lane for 200GBASE‑R with PAM4 line coding.
三、Specifications for FEC (Forward Error Correction) encoding. Requires option M8042A-0G9（表 3）
FEC encoding 100GBASE-R, 200GBASE-KP4
2×400GBASE-KP4
Reed-Solomon Code RS (544,514)
Pattern sequence These patterns from pattern library can be FEC encoded: Remote faults, Scrambled idle
Line coding PAM4
Symbol rate 53.125 GBd PAM4: 100GBASE (all PCS lanes), 200GBASE and 2×400GE (PCS
0→3 on
106.25 GBd PAM4: 200GBASE-R (clause
176, symbol multiplexing) (all PCS lanes)
FEC symbol error injection Post-FEC engine error insertion
条件：Pre-requisites M8042A with option 0G9
Figure 9. FEC encoding in M8042A (left) and FEC error insertion (right) shown in the M8070B software.
Pre-coder PAM4
1/ (1+D) mod4, can be switched on/off.
Follows IEEE 802.3 Clause
135.5.7.2. for PAM4 encoded lanes.
USB4 LFPS Generator
Low‑Frequency Periodic Signaling (LFPS) in USB4 consists of low‑speed electrical signaling bursts
transmitted on the high‑speed USB4 differential lanes when the link is not yet in normal data
transmission mode. LFPS uses low‑frequency square‑wave–like pulses (typically in the few‑MHz
range) that can be reliably detected before clock recovery and high‑speed equalization are
The USB4 LFPS Generator utility generates LFPS patterns with the M8070B software, allowing
configuration of cycles, period, duty cycle, pre-data, and idle duration. Supported by the M8042A
and M8045A modules, it handles USB4 Gen 2 (10 Gbps), Gen 3 (20 Gbps), and Gen
4 (25.6 GBd)
data rates. The LFPS Generator offers Calibration and Rx testing modes, controllable with Start and
条件：Figure 10. The USB4 LFPS generator utility shown in the M8070B software.
Trigger Output 1/2 (Trig Out 1, Trig Out
2)
The Trigger Output 1 and Trigger Output
2 connectors on the M8042A pattern generator module
provide programmable digital trigger signals that allow the BERT to be synchronized with external
instruments or system events during test and characterization. These outputs generate
timing‑accurate trigger pulses derived from internal BERT events, enabling precise correlation
between bit‑电平 behavior 和外部测量
条件：• Divided clock with dividers: o Max output frequency is 8.0 GHz, divider range 2 to 65000. o Minimum divider n is the next integer value above the symbol rate/ 8 GHz (Example: for a symbol rate of 53 GBd, n = 7, because it is the next higher integer of 53 / 8 = 6.625).
The trigger outputs can be used in one of the different modes:
条件：algorithmic pattern is used) o Pulse width: minimum 16 UI, maximum PRBS length.
• Pulse mode triggered by sequencer (only if memory pattern is used)
o Pulse width min
16 UI. Max block length
o Offset min 0. Offset Max block length
-1
• “Pulse on PRBS” mode (NRZ only). Matched pattern without ignoring defined bits (only if
The trigger signals are typically TTL/CMOS‑level digital pulses, intended for direct connection to
the trigger or external‑reference inputs of oscilloscopes, logic analyzers, spectrum analyzers, or
Amplitude
0.1 to 1.0 Vpp single-ended
Jitter injection The injected jitter is always the same as the jitter at the Data Out (excluding clk/2)
条件：1. High level voltage range= 2/3*Vterm – 0.9 V < HIL < Vterm + 2 V
2. Low level voltage range= 2/3 *Vterm – 1 V < LOL < Vterm + 1.9 V
Range
0 to 1000 UI with 1 UI resolution
Skew between trigger output and data output of same channel
460 ps maximum (measured)
Output voltage window –1 to 3 V
2
External termination voltage
–1 to 3 V
Connector type
3.5 mm, female
Control Input A/B (Ctrl In A, Ctrl In B)
条件：allow real‑time interaction between the pattern generator and external equipment or test logic.
deterministic timing, allowing tight integration into automated or system‑level test environments.
M8042A’s internal timing, ensuring repeatable and cycle‑accurate behavior.
Each control input can be selected as: sequence trigger, error insertion.
Control Input A and Control Input B on the M8042A provide external digital control interfaces that
These inputs enable external signals to control, gate, or switch internal M8042A functions with
The control inputs accept TTL/CMOS‑level digital signals and are sampled synchronously with the
Input voltage
–1 V to +3 V
Termination voltage
–1 V to +3 V
Termination voltage accuracy ± (25 mV
+1%)
Threshold voltage
–1 V to +3 V
Delay repeatability to data output
±512 UI maximum
Absolute delay to data output <
25 µs
Connector type
3.5 mm, female
Control Output A/B (Ctrl Out A, Ctrl Out B)
Control Output A and Control Output B on the M8042A provide programmable digital output
signals that reflect internal pattern‑generator events or states. They allow the M8042A to drive or
notify external equipment with precise, deterministic timing derived directly from the BERT’s
条件：automated test systems. These outputs provide a pulse or static high/low if used from sequencer.
The control outputs generate TTL/CMOS‑level digital signals and can be independently
configured, enabling flexible coordination with external instruments, DUT control circuitry, or
条件：1. When terminated with 50 Ω into GND. Doubles when operating into open.
Requires a 4-wire mini coax M8051A‑801 (also orderable as M8041-61601).
Output voltage window
–0.5 to 1.75 V
Delay to data output
±512 UI maximum
Connector type
3.5 mm, female
Link Interfaces Link 1/2 (Link 1, Link
2)
Link 1 and Link 2 are logical link interfaces within the M8050A BERT system that represent
independent, bidirectional test links between the transmitter (Tx) and receiver (Rx). The link
interface enables interactive, low‑latency link training (such as PCIe or USB requires) between a
pattern generator channel and the M8046A analyzer module.
Link 2 is available only with the two‑channel version of the M8042A.
Figure 11. Link interface
4-wire mini coax M8051A‑801.
Channel Clock Input 1/2 (Ch Clk In 1, Ch Clk
2)
Channel Clock Input 1 and Channel Clock Input
2 are used to supply the per-channel sampling
clock from the M8009A clock module to the M8042A pattern generator. These clock inputs
provide the timing reference required for precise symbol generation and deterministic operation at
条件：provide an independent clock connection for the second pattern generator channel.
Channel Clock Input 2 is available only on the two-channel version of the M8042A and is used to
Connector type
1.85 mm, female.
The following semi-rigid clock cables are supported for connecting the M8042A to the M8009A
• M8042A-801 – Clock Semi-rigid Cable for Pattern Generator M8042A, Channel
1 (also
orderable as M8042-61621)
• M8042A-802 – Clock Semi-rigid Cable for Pattern Generator M8042A, Channel
2 (also
orderable as M8042-61622)
Alternatively, a generic semi-rigid clock cable may be used, such as M8199A-810 – 450 mm
semi-rigid clock cable
1.85 mm (m) to 1.85 mm (m) (also orderable as M8199-61624, included in
the M8042A-810 cable kit).
Synchronization Input (Sync In)
条件：• M8042A-803 – Semi‑rigid synchronization cable, 3.5 mm (also orderable as M8042-61623).
The Sync In input is used to connect the M8042A pattern generator to the M8009A clock module
and provides a system-level synchronization reference. This input ensures deterministic alignment
and timing coherence between the clock subsystem and the pattern generator, enabling stable
operation and repeatable measurements, especially in multi-module or multi-channel
configurations. The synchronization signal is essential for coordinated pattern generation and
timing control within the M8050A BERT system architecture.
Connector type
3.5 mm, female.
The following semi‑rigid cable is supported for connecting the Sync In input of the M8042A to the
Sync Out of the M8009A clock module:
Local Bus Input/Output (LB In, LB Out)
条件：AXIe chassis, enabling coordinated operation and system-level synchronization.
Local Bus Input (LB In) and Local Bus Output (LB Out) provide local bus communication between
adjacent AXIe chassis in a multi-chassis M8050A BERT configuration. LB In is used to receive local
bus signals from the previous AXIe chassis, while LB Out forwards the local bus signals to the next
Connection is made using a
4-wire mini-coax local bus cable, M8051A-801 (also orderable as
M8041-61601).
Specifications for Patterns and Sequences
条件：stress conditions. Sequence control allows precise timing, looping, branching, and event-based
test cases, corner-case analysis, and repeatable compliance and characterization measurements.
The M8050A supports a wide range of built-in and user-defined patterns, including PRBS, fixed,
and custom binary patterns, enabling comprehensive receiver testing. Patterns can be flexibly
combined into programmable sequences to model realistic traffic, protocol behavior, and targeted
triggering to emulate complex system scenarios. This capability enables efficient automation of
Figure
12. Sequence example in the M8070B for the M8042A pattern generator and M8046A error detector
for PCIe 6.0
64 GT/s for the link training and LinkEQ receiver test.
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