LitePoint
z5211 双通道任意波形发生器 详细指标
2 通道 · 200MS/s 14bit · 14Vpp 入 50Ω · 四档贝塞尔滤波 · DDS 时钟
详细指标
指标取自 LitePoint 官方技术规格书(PDF)。该型号官方已标注 Discontinued(停产),本站仍保留其页面与指标供存量系统参考。
端口说明
• CH1 CH2:BNC | Channel N output
• POD 1 POD 2:Custom | Channel N accessory connector
• EXT IN:SMB (PXI/PXIe) | External input for trigger or reference
• EXT OUT:SMB (PXI/PXIe) | External output for trigger, reference or event
Outputs
• 通道数:Analog Outputs
• 连接器:BNC
• Analog Bandwidth:DC to 10 MHz (±0.1 dB Passband flatness) DC to 25 MHz (-1 dB bandwidth) DC to 50 MHz (-3 dB bandwidth)
• Lowpass Filters:50 MHz, 5-pole Bessel 10 MHz, 5-pole Bessel 1 MHz, 5-pole Bessel 100 kHz, 5-pole Bessel
• Slew Rate1:> 2 kV/μs into 50 Ω (50 MHz filter)
• Rise/Fall Time:<7 ns for 10 V step into 50 Ω (50 MHz filter)
• Range Adjust2 Into 50 Ω Into High Impedance:7.5 mVpp to 14 Vpp 15 mVpp to 28 Vpp Range independently adjustable for each output channel
• DC Offset Adjust Into 50 Ω Into High Impedance:≤ ±7 V ≤ ±14 V
• Output Voltage Limit3 Into 50 Ω Into High Impedance:|VAMP + VOFFS| ≤ 7 V |VAMP + VOFFS| ≤ 14 V
• Output Current Limit:±140 mA recommended operating maximum ±350 mA short circuit maximum
• Range Resolution4:0.5 mVpp
• Range Accuracy4 (25°C ambient):< ±(0.5% of range + 10 mVpp)
• Range Drift4:< ±1.5 mVpp per °C
• 输出阻抗:50 Ω typical
Digital-to-Analog Converter (DAC)
• 28.0 to 1.0:14.0 to 0.5 | 14 bits
• 0.9995 to 0.5:0.4995 to 0.25 | 13 bits
• 0.4995 to 0.25:0.2495 to 0.125 | 12 bits
• 0.2495 to 0.125:0.1245 to 0.0625 | 11 bits
• 0.1245 to 0.0625:0.062 to 0.031 | 10 bits
• 0.062 to 0.031:0.0305 to 0.0155 | 9 bits
• 0.0305 to 0.015:0.015 to 0.0075 | 8 bits
• DAC Resolution:14 bits (0.0061% of full-scale range)
• Waveform Length:Samples to 32 MiSamples per channel
• DAC Clock:DAC sample clocks generated by Direct Digital Synthesizers. All channels have independent or common DAC sample clocks.
• DAC Clock Rate:200 Samples/s to 200 MSamples/s
• DAC Clock Resolution:< 0.01 ppm or > 8 digits (i.e. 0.116 Hz from 20 MS/s to 200 MS/s)
• DAC Clock Sweep:Swept DAC clock rate: linear or log sweep See Sweep Mode for additional details
• DAC Clock Output:External Output: 100 Hz to 100 MHz common clock source
• DAC Clock Jitter:< 20 ps
• Channel-to-Channel Skew:< 500 ps (50 MHz filter)
• Channel-to-Channel Isolation:≥60 dB
• RMS Noise (with DAC clock above filter cutoff):≤ 1mV into 50 Ω (50 MHz filter)
• ≤ +20 dBm:100 kHz | < -73 dBc | < -52 dBc
• > +20 dBm:100 kHz | < -70 dBc | < -52 dBc
Horizontal
• Timebase Reference:10 MHz
• Timebase Reference Source:Internal TCXO, External Input, Backplane (PXI/PXIe)
• Internal TCXO Timebase:±2.5 ppm accuracy
• Timebase Output:External Output
Operation Modes
• 功能:Generate output continuously when initiated
• 功能:Generate a discrete number of cycles upon trigger event
• Number of Cycles:1 to 65535, programmable A cycle is one waveform period, or one arbitrary waveform sequence
• 功能:Toggle between two preloaded waveforms based upon modulation state. Enables Amplitude, Phase, Frequency Shift Keying, or Gated Output
• Modulation Source:External Input, Bus Trigger 0-7, Star Trigger (PXI/PXIe), Internal Trigger, Software
• 功能:Sweeps DAC clock rate for swept output signal frequency Programmable start frequency & stop frequency Programmable up, down, or up & down modes
• Sweep Types:Linear or Logarithmic
• Sweep Range:1000:1 maximum sweep frequency range (start-to-stop ratio)
• Sweep Time:1 ms to 100 s sweep time programmable 1 μs resolution
触发
• Trigger Source:External Input, Pattern, Software, TTL Trigger 0-7, Star Trigger, Internal Trigger
• Trigger Slope/Polarity:Positive or Negative
• Trigger Modes:Edge, Pattern
• Pattern Trigger Mode:Pattern match true or false
• Pattern Sources:External Input, TTL Trigger 0-7, Star Trigger
• Trigger Delay:Programmable delay after trigger event before start of waveform 0 to 6.5535 ms programmable 100 ns resolution
• Trigger Latency:< (20 DAC clock periods + 100 ns)
• Trigger Detection Jitter:±½ DAC clock period
• Internal Trigger:Programmable internal trigger source, 1 μs to 100 s period 100 ns resolution
• Trigger Timestamp:100 ns resolution, 1 second rollover
Arm
• 功能:Arm to qualify Trigger Event
• Source:External Input, TTL Trigger 0-7, Star Trigger, Software
• 极性:Positive or Negative
外部输入(前面板)
• 功能:Trigger Input, Timebase Reference Input, External Arm, External Modulation Input
• Absolute Maximum Input (no damage):≤ ± 5 V (DC + peak AC), CAT I
• Input Trigger Level Adjustment:-2 V to +2 V 0.5 mV resolution ≤ 20 mV accuracy 20 mV overdrive (input hysteresis)
• Input Bandwidth (-3 dB):≥ 250 MHz
• 输入阻抗:1 MΩ || 30 pF or 50 Ω ≤ ±2% accuracy
• 连接器:SMB
Sync Outputs
• 通道数:2
• Outputs:External Output, Bus Trigger 0-7
• Time Resolution:5 ns to 500 μs (200 MHz to 2 kHz) Synchronized to DAC clock
• 极性:Programmable high or low pulses
• Timing:Programmable location and width (in DAC clock samples)
外部输出(前面板)
• 功能:Sync Output, Trigger Output, Timebase Reference Output, Common DAC Clock/2 Output, Event Output, Programmable Clock Output, Programmable Pulse Output, Constant Level
• Output Event Source:Arm Event, Trigger Event, Generation Complete Event, Operation Complete Event, Master Summary Status Event
• 极性:High or Low Truth
• Programmable Event Pulse Width:20 ns to 163 ms 10 ns resolution
• Programmable Clock:Period: 26.667 ns to 100 seconds 50% Duty Cycle
• Programmable Pulse Pulse Repetition Interval Pulse Width:26.667 ns to 100 seconds 16.667 ns
• Output Level:TTL Compatible into ≥ 200 Ω ≥ ±24 mA Output Drive
• Common DAC Clock/2:Half the common DAC sample clock 100 Hz to 100 MHz
• Output Enable:Tri-State Output Capability
• 连接器:SMB
背板触发
• 功能:Multi-Instrument Synchronization Trigger, Event Output Signals
• Triggers:TTL Trigger 0-7
• Direction:Input or Output
• Source:Arm Event, Trigger Event, Generation Complete Event, Operation Complete Event, Master Summary Status Event, Constant Level
• 极性:High or Low Truth
• Programmable Event Pulse Width:20 ns to 163 ms 10 ns resolution
Standard Functions
• 频率:0.001 Hz to 50 MHz
• Initial Phase:0° to 360°
• 频率:0.001 Hz to 20 MHz
• Duty Cycle:0 to 100%
• Shape:Ramp Up or Down
• 幅度:±100% of Maximum Range
• Pulse Width:0 to (Period – 1 Data Clock cycle)
• Rise/Fall Time:(1 Data Clock cycle) to (Period – 2 Data Clock cycles)
• Initial Delay:0 to (Period – 2 Data Clock cycles)
• Sinc Frequency:Frequency to 50 MHz
• Standard Deviation:(1 Data Clock cycle) to (Period/2)
• Half Width:(1 Data Clock cycle) to (Period/2)
• Period:1 μs to 1000 s
• Noise Type:Uniform White
• Center Frequency:100 Hz to 50 MHz
• Modulation Source:Internal
• Modulation Frequency:Hz to smaller of 1 MHz or Center Frequency
• Modulation Depth:0 to 100%
• Modulation Shape:Sine, Square, Triangle, Ramp Up, Ramp Down
• Frequency Deviation:Hz to smaller of 1 MHz or Center Frequency
• Frequencies:100 Hz to 50 MHz
• Tone Resolution:100 Hz minimum
• Number of Tones:1 to 16
• Bit Rate Frequency:0.001 Hz to 20 MHz
• Word Length:4 to 64 bits
Waveform Sequences
• Sequence:Predefines up to 8 sequences of arbitrary waveforms 2 to 4,096 waveform stages in sequence Each waveform repeated 1 to 65535 times within stage Waveform stages from waveform library and reference channels Each waveform stage has unique waveform handle and loop number Amplitude, offset and DAC sample rate apply to entire sequence
• Waveform Library:Predefined set of arbitrary waveforms Up to 4,096 waveforms in waveform library Total arbitrary waveform library memory limited to 8 MiSamples (16 MiB)
Reference Channels
• Reference Channels:Quantity 4
• Reference Storage:Non-volatile memory storage
• Reference Data:KiSample maximum waveform size 32-bit resolution
Waveform Operations
• Upload:Waveform memory written by host Ping-pong buffers enable upload during active waveform generation
• Download:Waveform memory read by host
• Copy:Waveform memory copied front one location or type to another
• Invert:Waveform DAC codes inverted (2s compliment)
• Scale:Waveform DAC codes linearly adjusted by scale factor
• Waveform Data Formats:16-bit signed integer 32-bit floating point Intel or Motorola Byte Order
仪器存储状态
• 功能:Non-volatile storage of instrument setup configuration
• Stored States:State 0 is Reset State Power-On State programmable
指示灯
• RDY (Ready):OFF: Hardware Failure ON: Unit has passed power-up self-diagnostics TOGGLE: Unit has an error pending in error queue
• HST/LAN (Host):OFF: Interface fault ON: Normal interface operation TOGGLE: Device identify enabled
• TRG (Trigger):OFF: Trigger event not detected ON/PULSE: Trigger complete event detected
• ACT (Active):OFF: Instrument Idle ON/PULSE: Waveform generation initiated
PXI 接口
• PXI Slot Compatibility:PXI Standard Slot and PXIe Hybrid Slot Compatible
• PXI Timing & Triggering Signals (XJ4 Connector):PXI_TRIG[0:7] input/output PXI_STAR input PXI_CLK10 input
PXIe 接口
LitePoint官方渠道
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• 联系方式与销售咨询
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• 地址
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• 地址
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授权分销商
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• 地址
Room 3006, 158 Yixian Road,Hongkou District, Shanghai, China
• 电话 +86 13681973678
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• 地址
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• 地址
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• 地址
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• 地址
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• 地址
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