LitePoint
z482 12 通道数字 IO 模块 详细指标
12 通道 · 每通道独立方向 · 每通道 PMU · 200Mbps · 通道间偏斜 ±500ps
详细指标
指标取自 LitePoint 官方技术规格书(PDF)。该型号官方已标注 Discontinued(停产),本站仍保留其页面与指标供存量系统参考。
引脚定义
• Number of data pins:12 pins of Pin Measurement unit (PMU) enabled
• Direction control of data pins:Per pin
• Number of remote sense pins:12 | All PMU-enabled pins have remote sense capability
• Generation Signal Type:Single-ended, ground reference
• Programmable generation voltage levels:Drive Voltage High Level (VIH) Drive Voltage High Level (VIL) Drive Termination Voltage (VT)
• Generation voltage range:-2 V to 6 V
• 精度:0.25% of value + 20 mV
• Generation voltage resolution:100 μV
• Generation voltage swing:400 mV to 8 V
• 输出阻抗:50 Ω | Nominal
• Maximum allowed DC drive per pin:± 50 mA | Nominal
• Data pin tristate control:Per pin, per cycle
• Pin power-on state:Drivers disabled, high impedance (tri-state)
• Output protection:The device can sustain a short to any voltage between -2 V and 6 V provided that you observe the maximum drive strength limitations
• Acquisition Signal Type:Single-ended, ground reference
• Programmable acquisition voltage levels:Compare High Level (VOH) Compare High Level (VOL) Voltage Termination (VT)
• Acquisition voltage threshold:-2 V to 7 V
• 精度(VOH, VOL):0.25% of value + 20 mV
• 精度(VT):0.25% of value + 20 mV
• Termination voltage resolution:600 μV
• Termination voltage range:0 V to 6.5 V
• Minimum detectable voltage swing:10 mV
• 输入阻抗:High Impedance or 50 Ω terminated into VT
• Input protection:The device can sustain a short to any voltage between -2 V and 6 V provided that you observe the maximum drive strength limitations
• Programmable levels:Current Source (IOH) Current Sink (IOL)
• Load:Range | Resolution
• Number of pins:6
• Programmable levels:Force voltage | HV = (VT + 1) x 2
• Force Voltage:Range | Accuracy
• Clamp Voltage Range High Side (VCH):-1.0 V to 6.0 V
• Clamp Voltage Range Low Side (VCL):-1.5 V to 5.0 V
• Termination Voltage (VT):-2.0 V to 6.0 V
• Programmable levels:Force voltage (FV) Force current (FI) Voltage clamp high (VCH) Voltage clamp low (VCL) | Voltage clamps are only active when forcing current
• Force voltage (FV):Range | Accuracy | Resolution | Maximum accuracy at the sense location with 1 50 Hz PLC aperture
• Force voltage rise time (no load):Range | Settling time | Typical rise time from 10% to 90% of the final value, 6 V
• Force voltage rise time (1 nF load):Range | Settling time | Typical rise time from 10% to 90% of the final value, 6 V
• Load capacitance:Range | Capacitance | These value represent the allowed load capacitance through a 1m SHC68-C68-D4 VHDCI cable to ensure a well-behaved transient response, < 300 μs rise time
• Aperture time range:1.25 μs to 200 ms
• Aperture resolution:1.25 μs
• Measure voltage:Range | Accuracy | Resolution | Maximum accuracy at the sense location with 1 50 Hz PLC aperture
• Measure current:Range | Accuracy | Resolution | Maximum accuracy at the sense location with 1 50 Hz PLC aperture
• Voltage clamp high (VCH):Range | 0 V to 6 V
• Voltage clamp low (VCL):Range | -2 V to 4 V
• Maximum temperature at PPMU pin under Full Load:85 °C | Fan set to HIGH speed.240 Ω / 1 W resistor is connected across each PMU channels FH and FL for all 12 pins. DVCI at 6 V / 25 mA (12 hours duration).
Timing Specifications
• Vector clock source:Onboard Clock
• 频率范围:1 kHz to 200 MHz
• Frequency resolution:<0.1 Hz
• 频率准确度:0.015% of value
• Maximum data rate per pin:200 Mbps
• Maximum data pin toggle rate:100 MHz
• Data pin to pin skew:Maximum: ±500 ps
• Output self-tune delay:—
• Maximum data pin toggle rate:100 Mhz
• Data position mode:Delay from sample clock rising edge
• Input data delay frequency:All supported frequencies
• Input delay adjustment:± 25 Sample clock cycles expressed as a time in seconds
• Input self-tune delay:1 ns
• Input data delay resolution:11 ps
Waveform Specifications
• On-board memory size (generation):Mbit/pin
• On-board memory size (acquisition):Mbit/pin | History RAM
• Generation mode:Clock mode | Generate continuous clock outputs
• Number of vector set:32
• Number of timing set:32
• Maximum data rate:200 Mbps | This applies to all pins
触发
• Sources:PXI trigger lines | PXI_TRIG[0:7] PXI_STAR PXI_LBL6 PXI_LBR6 PXIE_DSTARA PXIE_DSTARB
• 极性:High, Low, Rising, Falling | Configurable
• Pulse Width:≥ 200 ns
• Sources:PXI trigger lines | PXI_TRIG[0:7] PXI_STAR PXI_LBL6 PXI_LBR6
• 极性:Active High
• Pulse Width:1 μs to 10 ms | Configurable
MIPI RFFE
• Number of MIPI RFFE Controllers:4 | 2 MIPI RFFE controllers available for each pin group
• Full-Speed Clock Frequency:Minimum | 32 kHz
物理与环境
• 尺寸:1 slot 3U PXI Express Instrument
• Operating temperature range:23° C ± 10° C
• 校准周期:6 months
• Output Front Panel Connector:68 position VHDCI receptacle
资源下载
以上规格取自 LitePoint 官方技术规格书(PDF)与官网产品页;标注「典型」的为厂家典型值。
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